Nios II Multicycle Processor + FPGA Stopwatch
VHDL hardware-timer peripheral with IRQ generation, Nios II assembly ISRs, integrated into a multicycle Nios II processor: building blocks for an FPGA stopwatch on the Gecko4Education board.
Multicycle Nios II processor with interrupt support, plus the peripherals around it. Built across four labs toward an FPGA stopwatch on the Gecko4Education board. Lab 1: hardware timer peripheral in VHDL with memory-mapped control/status/counter/period registers and IRQ when the counter hits zero. Lab 2: interrupt-service routines in Nios II assembly for the timer and the buttons. Lab 3: IRQ support added to the multicycle processor. Lab 4: stitched together into the working stopwatch.
ModelSim and Quartus toolchain. CS-307 Computer Architecture 2 at EPFL.